In PON (Passive Optical Network) employed by an FTTH (Fiber To The Home) system as a high-speed broad-band optical transmission method, an OLT (Optical Line Terminal) that accommodates a plurality of users on the station side and an ONU (Optical Network Unit) that terminates an optical subscriber line on the user side are connected via an optical fiber so as to bidirectionally transmit signals.
In case of connection of a new ONU, if the optical reception circuit of the OLT has no noise masking function of preventing unnecessary noise output in the absence of optical input, the access controller connected to the subsequent stage of the analog front end needs to determine, by a specific algorithm, whether a received optical signal is noise or an optical signal from the newly connected ONU. Hence, the cost increases, and communication control becomes inefficient as the upper layer grows complicated.
On the other hand, there is provided, for the optical reception circuit of the OLT, a technique of causing an optical signal cutoff detection circuit to determine, based on an electrical signal output from a trans-impedance amplifier (TIA), the presence/absence of input of an optical signal and preventing unnecessary noise output from the optical receiver in the absence of an optical signal (for example, see patent literature 1).
As shown in FIG. 10, in an optical receiver 200, an optical signal Pin received by a photodiode PD is photoelectrically converted into a photocurrent signal Iin and amplified by a trans impedance amplifier TIA serving as a preamplifier. An electrical signal Tout from the trans impedance amplifier TIA is input to a limiting amplifier LA serving as a post-amplifier, amplified so as to change the optical signal Pin having a different strength to an electrical signal having a predetermined amplitude, and output as a reception output Rout. A waveform shaping circuit such as a CDR (Clock Data Recovery) or a timing adjustment circuit is normally connected to the subsequent stage of the limiting amplifier LA so as to extract a clock signal from the data signal and perform waveform shaping to obtain a digital signal easy to handle.
On the other hand, an optical signal cutoff detection circuit (LOS: Loss Of Signal) 20 for determining reception of the optical signal Pin is provided at the subsequent stage of the trans impedance amplifier TIA in parallel to the limiting amplifier LA. The optical signal cutoff detection circuit 20 generates a signal cutoff detection signal LOS representing whether the optical signal Pin having a sufficient signal strength is received, thereby detecting a communication error or performing squelch circuit control to cut off noise output from the limiting amplifier LA under no-signal conditions.
In the optical signal cutoff detection circuit 20, only when the optical signal Pin is received, a comparator 21 outputs a comparison output signal Cout. An SR latch 22 holds the comparison output signal Cout and converts it into the signal cutoff detection signal LOS formed from a DC signal. Holding of the signal cutoff detection signal LOS in the SR latch 22 is canceled by a reset signal RESET. For example, in burst communication represented by the PON system, a PON control IC can output the reset signal RESET at the end of burst packet reception.
Hence, using the signal cutoff detection signal LOS as the output control signal of the limiting amplifier LA to, for example, control squelch and closing the squelch from reception of the reset signal up to reception of the next burst signal make it possible to prevent noise output from the limiting amplifier LA. When the burst signal is received, the squelch can be opened to return to a normal reception state.
The comparator 21 shown in FIG. 11 includes a bias circuit 21A, a first-stage amplification circuit 21B, a first-stage emitter-follower circuit 21C, and a second-stage amplification circuit 21D.
A noninverted signal Tout+ and inverted signal Tout− of the electrical signal Tout input from the trans impedance amplifier TIA are AC-coupled to the bias circuit 21A via coupling capacitors C. Since the coupling capacitor C is a differentiating circuit, the differential waveforms of the noninverted signal Tout+ and inverted signal Tout− are input to a pair of differential transistors Q1 and Q2 of the first-stage amplification circuit 21B, respectively.
When load resistors R5 and R6 of the pair of differential transistors Q1 and Q2 have values different from each other, each output of the first-stage amplification circuit 21B has an offset voltage at the DC level.
Hence, unless the noninverted signal Tout+ and inverted signal Tout− having sufficient amplitudes are input, the output amplitude of the first-stage amplification circuit 21B is insufficient, and no differential signals can be formed, that is, the noninverted output from the transistor Q1 and the inverted output from the transistor Q2 do not cross. For this reason, the second-stage amplification circuit 21D connected via the first-stage emitter-follower circuit 21C does not output the comparison output signal Cout, and the signal remains at Low level.
On the other hand, if the noninverted signal Tout+ and inverted signal Tout− having sufficient amplitudes are input, the noninverted output from the transistor Q1 and the inverted output from the transistor Q2 cross. Hence, High level and Low level corresponding to the intersections alternatively appear as the comparison output signal Cout.
Since the SR latch 22 holds the comparison output signal Cout, the High level signal is continuously output as the comparison output signal Cout upon, for example, receiving the optical signal Pin. As the feature of this circuit, therefore, once the High level signal is output as the comparison output signal Cout, that level is held. It is therefore possible to implement the high-speed optical signal cutoff detection circuit 20 that immediately responds to signal reception.